Preparing Spec Control Drawings

1. Part size dimensions with tolerance, scale, units and smallest feature size clearly noted.
2. Metal layers must include the following details by order. Thickness and tolerance must be listed:

   Resistor Layer	50Ω/sq. TaN, TCR -100±50ppm/°C
   Conductor Layer Tungsten-Titanium (WTi): Nickel (Ni): Gold (Au):	500Å ± 100 2,000Å ± 500 100µ" ± 25µ"
   Solder Layer	4±1µm Pre-deposited 73/27 AuSn
   Ground Plane Tungsten-Titanium (WTi) Gold (Au):	500Å ± 100 100µ" ± 25µ"

3. Substrate thickness, tolerance and finish must be identified:

   Alumina, as-fired	99.6%
   Thickness	0.025"±0.002"
   Surface Finish	<4µ" CLA
   Camber	0.001"/"

4. Specialty inspection requirements should be listed (i.e. bake testing, TCR).
5. Customer name, customer part number and revision level must be listed on SCD.
6. Resistance and/or capacitance charts should be provided:

   Resistor	Nominal (Ω)	TOL	Length	Width
   R1, R4	18.8	+5/-20%	.0150	.0400
   R2, R5	15	+5/-20%	.0150	.0500
   R3, R6	12.5	+5/-20%	.0150	.0600
   R7, R10	16.5	+5/-20%	.0150	.0450
   R8, R11	25	+5/-20%	.0150	.0300
   R9, R12	50	+5/-20%	.0150	.0150
   R13, R16	50	+5/-20%	.0450	.0450
   R14, R17	16.5	+5/-20%	.0150	.0450
   R15, R18	11	+5/-20%	.0100	.0450
   R19, R22	25	+5/-20%	.0200	.0400
   R20, R21	12.5	+5/-20%	.0100	.0400

7. Additional layers thickness and tolerance must be called out (i.e. SiN, polyimide).

   Dielectric layer

   20,000Å ± 5,000Å Si3N4

8. Additional layer properties must also be called out (i.e. 80/20 Au/Sn versus 70/30 Au/Sn).

   Solder layer

   4±1µm Pre-deposited over 73/27 AuSn

9. All pullbacks should be identified and dimensioned.
10. Plating requirements must be defined.
11. Front to back registration tolerance should be listed when applicable.
12. Camber requirements should be listed.
13. Filled vias must specify material Eg: Gold, Copper Tungsten, etc.
14. Plated through-hole and via locations, diameters, and tolerances should be dimensioned.